1. Field of the Invention
The present invention relates to an image display device easily realizing a larger number of pixels and, more particularly, to an image display device suitable for achieving higher precision.
2. Description of the Prior Art
Two prior arts will be described hereinbelow with reference to FIGS. 9 to 12.
FIG. 9 is a diagram showing a general configuration of a light emitting display device as a first prior art. In a display area 200, pixels 201 are provided in a shape of a matrix. To the pixel 201, a signal line 202 and a gate line group 203 are connected. One end of the signal line 202 is connected to a signal-current generating circuit SGEN, and one end of the gate line group 203 is connected to a scanning circuit SCN. In practice, a number of pixels 201 are provided in the display area 200. However, for simplification of the drawing, only one pixel is shown in FIG. 9. In the signal line 202, parasitic capacitance Cs exists. Although a power source line and a common ground electrode are also provided for the pixel 201 as will be described later, they are not shown in the drawing. Although the gate line group 203 is constructed by a plurality of gate lines in reality, only one line is shown for simplification.
The operation of the prior art shown in FIG. 9 will now be described. The scanning circuit SCN sequentially scans the gate line group 203, thereby selecting a pixel row to which a display signal current Isig is passed. Synchronously, the signal-current generating circuit SGEN supplies the display signal current Isig to the signal line 202, so that the display signal current Isig is passed to the selected pixel 201.
The structure and operation of the pixel 201 will be described with reference to FIG. 10.
FIG. 10 is a circuit configuration diagram of the pixel 201. Each of the pixels 201 is provided with an organic electro-luminescent (EL) device 210 as a light emitting device. The cathode terminal of the organic EL device 210 is connected to a common ground 217. The anode terminal is connected to a power source line 216 via a channel of a drive TFT (Thin-Film-Transistor) 211 and a power source switch 215. The source terminal side of the drive TFT 211 is further connected to the signal line 202 via a write switch 214. Between the source terminal and the gate terminal of the drive TFT 211, a signal electric-carrier storage capacitor Csig is provided. Between the drain terminal and the gate terminal, a reset switch 212 is provided. The power source switch 215, write switch 214, and reset switch 212 are scanned by the gate line group 203.
The operation of the pixel shown in FIG. 10 will now be described. At the time of writing the display signal current Isig to the pixel 201, by the gate line group 203, the power source switch 215 is set to an off state, and the write switch 214 and the reset switch 212 are set to an on state. When the display signal current Isig is passed to the signal line 202 at this timing, the display signal current Isig flows into the organic EL device 210 via the channel of the drive TFT 211. At this time, a gate voltage difference corresponding to the value of the passed display signal current Isig occurs between the source terminal and the gate terminal of the drive TFT 211. After that, when the write switch 214 and the reset switch 212 are switched to the off state, a gate voltage signal corresponding to the value of the passed display signal current Isig which is generated between the source terminal and the gate terminal of the drive TFT 211 is held as it is in the signal electric-carrier storage capacitor Csig.
The above is the writing operation. After that, when the power source switch 215 is turned on by the gate line group 203, a voltage from the power source line 216 is supplied to the source terminal of the drive TFT 211, so that the drive TFT 211 applies the display signal current Isig corresponding to the gate voltage signal held in the signal electric-carrier storage capacitor Csig to the organic EL device 210. By the application, for the subsequent display period, the organic EL device 210 continuously illuminates with predetermined brightness.
Such a prior art is described in detail in, for example, “Digest of Technical Papers, IEDM 98, pp. 875-878).
The first prior art, however, has a problem such that it takes much time to pass a signal current to a selected pixel and increase in the number of pixels of the light emitting display device cannot be addressed.
Generally, a signal current used for driving the organic EL device in one pixel is 500 nA or less. When display precision of 50 gradations is assumed, writing with the minimum signal current of 10 nA is necessary. However, the parasitic capacitance Cs of a signal line is generally 10 pF or larger. For example, to write a signal shift of 100 mV with a signal current of 10 nA, a time constant is as large as 100 μsec. When time which is three times as long as the time constant is assumed for writing, 300 μsec is necessary to write pixels in one row. Consequently, when moving picture display of 60 frames/sec is assumed, the maximum number of pixel rows which can be written in a real time manner is only 56.
A second prior art to be described with reference to FIGS. 11 and 12 has been proposed to solve such a problem.
FIG. 11 is a diagram showing a general configuration of a light emitting display device as the second prior art. Since the configuration and operation of the second prior art are almost the same as those of the first prior art described above with reference to FIG. 9, the same reference numerals are given to similar components and the description will not be repeated. The second prior art is different from the first prior art with respect to the point that the signal-current generating circuit SGEN passes a signal current of Isig×K to the signal line 202. The signal current Isig is the value of display signal current for driving the organic EL device 210.
The structure and operation of a pixel 201A will be described with reference to FIG. 12.
FIG. 12 is a circuit configuration diagram of the pixel 201A. Each pixel 201A is provided with the organic EL device 210 as a light emitting device. The cathode terminal of the organic EL device 210 is connected to the common ground 217, and the anode terminal is connected to the power source line 216 via a channel of the drive TFT 211. The source terminal and the gate terminal of the drive TFT 211 are connected to the source terminal and the gate terminal of the write TFT 228, respectively. Between the source terminal and the gate terminal of the drive TFT 211, the signal electric-carrier storage capacitor Csig is provided. Between the drain terminal and the gate terminal of the write TFT 228, a reset switch 222 is provided. The drain terminal of the write TFT 228 is connected to the signal line 202 via a write switch 224. The write switch 224 and the reset switch 222 are scanned by the gate line group 203.
In the second prior art, it should be noted that the drive TFT 211 and the write TFT 228 have a so-called pair transistor configuration in which their source terminals and gate terminals are commonly connected, and the W/L (gate width/gate length) ratio of the write TFT 228 is designed to be K times as high as that of the drive TFT 211.
The operation of the pixel shown in FIG. 12 will now be described. At the time of passing the display signal current Isig×K to the pixel 201A, by the gate line group 203, the write switch 224 and the reset switch 222 are set to the on state. When the display signal current Isig×K is passed to the signal line 202 at this timing, the display signal current Isig×K flows from the power source line 216 to the signal line 202 via the channel of the write TFT 228. At this time, a gate voltage difference corresponding to the value of the passed display signal current Isig×K occurs between the source terminal and the gate terminal of the write TFT 228. At the same time, between the source terminal and the gate terminal of the drive TFT 211, a gate voltage difference corresponding to the value of the passed display signal current Isig occurs.
The reason why the value of the signal current Isig which is generated in the drive TFT 211 is 1/K of the signal current value of the write TFT 228 is because the W/L (gate width/gate length) ratio of the write TFT 228 is designed to be K times as high as that of the drive TFT 211 as described above.
When the write switch 224 and the reset switch 222 are switched to the off state, the gate voltage signal corresponding to the value of the passed display signal current Isig×K which is generated between the source terminal and the gate terminal of the write TFT 228 is held as it is in the signal electric-carrier storage capacitor Csig. At this time, the drive TFT 211 applies the display signal current Isig to the organic EL device 210 in correspondence with the gate voltage signal held in the signal electric-carrier storage capacitor Csig. By the application, for the subsequent display period, the organic EL device 210 continuously illuminates with predetermined brightness.
Such a prior art is described in detail in, for example, “Digest of Technical papers, SID 01, pp. 384-387”.